The present invention is related to the use of non-ferrous alloys as lead frame materials in Multi-Layer Ceramic Capacitors.
As the trend to reduce the size of electronic devices continues, the need to increase the electrical performance, mechanical robustness, and improve the efficiencies of each component becomes more critical. The performance and efficiencies of capacitors is no less important than many of the more active devices. Not only do the inefficiencies of the capacitor affect the performance of the circuits, they also affect the thermal management problem that is created by the increased generation of heat due to the applied voltage and current. The continued desire to decrease the size of electronic devices places an ever increasing pressure on component manufacturers to minimize the size of components while maintaining or increasing performance.
Multi-Layer Ceramic Capacitors (MLCC), which are the focus of this invention, are under significant pressure to minimize size due to their widespread use and superior performance when compared to many other types of capacitor.
The relationship between capacitance, electrode overlap and active thickness is given in Equation 1.C=∈0∈rAN/t  Equation 1where:C=Capacitance (F);∈0 is a constant which is the Permittivity of Free Space=8.854×10−12 (F/m);∈r=dielectric permittivity;A=overlap area of active electrodes (m2);N=number of actives; andt=Active thickness (m).It can be seen from Equation 1 that for any given dielectric, with a characteristic dielectric permittivity, capacitance can be raised by increasing the area (A), reducing the active thickness (t), increasing the number of layers (N) or some combination thereof.
Increasing the overlap area of the capacitor can generally be achieved by increasing the length and width of the capacitor which necessarily increases the pad size area required to mount the capacitor. This is contrary to efforts related to miniaturization.
Decreasing the active thickness, t, is limited by practical considerations such as the dielectric breakdown withstanding voltage of the dielectric as well as the production process used. Therefore, the voltage rating for the MLCC is lowered with reduced thickness which is undesirable.
Increasing the number of layers raises the thickness of the final part in the vertical dimension which is undesirable. Furthermore, there is an economical limit with regards to the number of layers that can be added to the capacitor in the vertical axis. It can become more economical to consider stacking two or more capacitors together that are electrically connected through the use of a lead frame. There are also applications where it is desirable to attach leads to a single chip to reduce tensile stresses on the MLCC during substrate flexing. Typically, single chips are mounted directly to the board, a process known to the industry as “surface mount”.
When selecting high performance capacitors it is necessary to identify those that provide the optimum electrical performance for the application. Low ESR and low ESL are desirable because under an electrical load the conversion of electrical energy to heat is minimized resulting in the lowest power loss. In MLCC's the dielectric material is an important factor. Ferroelectric class 2 materials such as X7R and X5R (EIA designation) have high dielectric constants and contain domains that move when an AC voltage is applied. This results in domain wall heat loss and is an additional source of concern compared to class 1 C0G dielectrics that are paraelectric with no domains. The class 1 type materials have far lower dielectric constants so for many applications the designer must use a class 2 dielectric to achieve the desired capacitance. By stacking more than one capacitor in a lead frame, as shown in FIG. 1, the capacitance can be doubled whilst using the same circuit board pad size. The lead frame, and connection thereto, has been a limiting component of stacked capacitors and a source of the inefficiencies in this approach.
Ceramic capacitors are one type of many capacitor designs available to designers. One physical property of ceramic capacitors is that they are extremely strong when subjected to compressive stresses but relatively weak under tensile loading. This becomes an important physical trait that designers must contend with when capacitors are attached to non rigid substrates such as typical laminate circuit boards made from a composite of fiberglass and epoxy, commonly known in the industry as FR-4, G-10, and CEM 1-4 series, etc. When ceramic capacitors are mounted to these non rigid substrates the forces induced into the ceramic, during board flexure, are critical and may cause the capacitors to crack or break due to the tensile forces induced into the capacitor body.
One design option available to minimize the stress induced into the ceramic capacitors body due to the flexing of the substrate is to add leads to the capacitor that actually absorb the flexure of the substrate thus minimizing the tensile stresses induced to the body of the ceramic capacitor. These leads are made from a conductive material with surface finishes that are compatible with the capacitor's terminations and the material used to attach the lead to the capacitor terminations generally referred to in the industry as solder, which can be of a Sn/Pb based alloy, or Lead (Pb) free solders, such as the Sn/Ag/Cu(SAC) alloys, or other alloys that provide acceptable processing for lead attach processes.
When considering the lead frame material, it has been taught in the art that materials with Coefficients of Thermal Expansion (CTE) that are ideally less than the ceramic must be used so that when the device is exposed to temperature cycling, the capacitor is always in a state of compression. Several preferred alloys exist that fit these physical properties. Such alloys common to the industry are the Ni/Fe alloys known as Alloy 42 which consists of approximately 42% Ni 58% Fe. Kovar® which consist of nickel, iron and cobalt is another common choice. Alloy 42 is the preferred material since it's is more economical than the Kovar® alloys. U.S. Pat. Nos. 6,310,759 and 6,523,235 describe the preference of using Alloy 42 due to its lower CTE than ceramic. U.S. Pat. No. 6,081,416 states that the CTE of ceramic needs to be 25% greater than the lead frame. These patents also identify the importance for components to be able to operate in temperature range of −55° C. to +150° C., an accepted industry standard for electronics, although some variations to this standard exist, such as −55 C to +125 C, or −40 C to +150 C, depending on the specific product application.
While the Ni/Fe alloys offer favorable mechanical properties their magnetic properties as well as low electrical conductivity are inherent electrical disadvantages. Both the lower conductivity and magnetic properties of the materials are detrimental to optimization of capacitor performance.
As realized from the foregoing there has been an ever increasing need to improve capacitor performance. Such an improvement is provided herein.